DREAMCloud Workshop 2016

DREAMCloud 2016
2nd International Workshop on Dynamic Resource Allocation and Management
in Embedded, High Performance and Cloud Computing


HiRES 2016
4th Workshop on High-performance and Real-time Embedded Systems

Jan 19th 2016

Co-Located with HiPEAC 2016
Prague, Czech Republic

DREAMCloud is a workshop aiming to encourage technical and scientific exchanges
between senior academics, young researchers and industrialists in the area of
dynamic resource management in embedded, high performance and cloud computing.
It has strong emphasis on performance predictability and energy
efficiency. It aims to foster cooperation across the different domains by emphasising the
latest trends bringing together the respective research communities:

- embedded systems are increasingly complex, having to cope with dynamic
workloads, and using multiprocessor and communication-centric platforms, while
fulfiling strict timing and energy requirements;

- high-performance and cloud computing critically need to address fundamental
problems in energy efficiency and performance predictability, despite having
little or no a priori knowledge about their workloads.

The second DREAMCloud Workshop and the fourth HiRES workshops will be organised
together and will be co-located with the HiPEAC 2016 Conference in Prague,
Czech Republic (https://www.hipeac.net/2016/prague/).


Leandro Soares Indrusiak - University of York, UK
Alexey Cheptsov - High Performance Computing Center Stuttgart (HLRS), DE
Luis Miguel Pinho - CISTER, IPP, PT


14:00 Opening and Invited talk: Akash Kumar (TU Dresden)

Design and Evaluation of Reliability-oriented Task Re-Mapping in MPSoCs using Time-Series Analysis of Intermittent faults

Abstract: A large number of hardware faults are being caused by an increasing number of manufacturing defects and physical interactions during operation. This poses major challenges for the design and testing of modern Multiprocessor System-on- Chips (MPSoCs). Intermittent faults constitute a major part of hardware faults and their fault rates can be used as an indicator of the wear-out in a Processing Element (PE). We propose a run-time task re-mapping method that uses this information to improve the useful lifetime of MPSoCs. We also propose a scenario-aware system-level fault injection technique for intermittent faults to evaluate system-level design techniques in MPSoCs. Our performance results conclusively show that our strategy significantly scales on reliability metrics with respect to number of PEs. Specifically, we show that our method can achieve an increase in lifetime of up to 16% and tolerate up to 30% more faults than state-of-the-art techniques.

14:35 Session 1: Dynamic Resource Management in HPC and Cloud Computing

Monitoring in the Clouds: Comparison of ECO2Clouds and EXCESS Monitoring Approaches
Pavel Skvortsov, Dennis Hoppe, Axel Tenschert and Michael Gienger (HLRS, Universitaet Stuttgart, DE)

A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud Infrastructures
Roman Ursu, Khalid Latif, David Novo, Manuel Selva, Abdoulaye Gamatie and Gilles Sassatelli (LIRMM - University of Montpellier, FR)
Dmitry Khabi and Alexey Cheptsov (HLRS, Universitaet Stuttgart, DE)

Bidding policies for market-based HPC workflow scheduling
Andrew Burkimsher and Leandro Soares Indrusiak (University of York, UK)

Improving virtual host efficiency through resource and interference aware scheduling
Evangelos Angelou, Konstantinos Kaffes, Athanasia Asiki, Georgios Goumas and Nectarios Koziris (National Technical University of Athens, GR)

15:35 Coffee break

16:00 Session 2: Predictable Resource Management in Multiprocessor Embedded Systems

Benchmarking, System Design and Case-studies for Multi-core based Embedded Automotive Systems
Piotr Dziurzanski, Amit Singh and Leandro Soares Indrusiak (University of York, UK)

Holistic Approach for Fault-Tolerant Network-on-Chip based Many-Core Systems
Siavoosh Payandeh Azad, Behrad Niazmand, Jaan Raik, Gert Jervan and Thomas Hollstein (Tallinn University of Technology, EE)

Design and validation of a multi-core embedded platform under high performance requirements
Vittoriano Muttillo (University of L'Aquila, IT)

Guaranteeing predictable parallel behavior in the P-SOCRATES architecture
Luis Miguel Pinho (CISTER - IPP, Porto, PT)

17:00 Invited talk: Gerard Rauwerda (RECORE)

Many-core processor architectures; fault-tolerance and programmability

Abstract: Massive many-core SoCs – like many other designs – are often designed with the focus on the hardware. The programming models for these complex many-cores often come as an afterthought and programmers have to make do with what is designed into the hardware. This gives many-core programming a reputation of being a programmer’s nightmare. In this talk, Gerard will present Recore's FlexaWare approach. FlexaWare® is a flexible and scalable embedded processing platform that unites easy programming and heterogeneous many-core system complexity. The embedded platform combines hardware, a runtime and a software development environment. Also, he will explain Recore's contribution to several European FP7/H2020 research projects with respect to many-core programming issues as well as fault-tolerance.

17:30 Closing

You need to be a member of DreamCloud Project to add comments!

Join DreamCloud Project

Email me when people reply –

Project Partners